1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
Liquid crystal display (“LCD”) devices are driven based on electro-optical characteristics of a liquid crystal material. The liquid crystal material has an intermediate state between a solid crystal and an isotropic liquid. The liquid crystal material is fluid like the isotropic liquid, and molecules of the liquid crystal material are regularly arranged like the solid crystal. An alignment direction of the liquid crystal molecules depends on the intensity or the direction of an electric field applied to the liquid crystal molecules. Light passes through the LCD device along the alignment direction of the liquid crystal molecules. By controlling the intensity or the direction of the electric field, the alignment direction of the liquid crystal molecules changes, and images are displayed.
Active matrix liquid crystal display (“AMLCD”) devices, which include thin film transistors as switching devices for a plurality of pixels, have been widely used due to their high resolution and ability to display fast moving images.
Generally, an LCD device includes two substrates, which are spaced apart and facing each other, and a liquid crystal layer interposed between the two substrates. Each of the substrates includes an electrode. The electrodes from respective substrates face one the other. An electric field is induced between the electrodes by applying a voltage to each electrode. The alignment direction of liquid crystal molecules changes in accordance with a variation in the intensity or the direction of the electric field. The direction of the electric field is perpendicular to the substrates. The LCD device has relatively high transmittance and a large aperture ratio.
However, the LCD device has narrow viewing angles. To increase the viewing angles, various modes have been proposed. Among these modes, an IPS mode of the related art will be described with reference to accompanying drawings.
FIG. 1 is a schematic cross-sectional view of an IPS mode LCD device according to the related art.
In FIG. 1, the IPS mode LCD device according to the related art includes a lower substrate 10 and an upper substrate 40, and a liquid crystal layer LC is interposed between the lower substrate 10 and the upper substrate 40.
A thin film transistor T, a common electrode 18 and a pixel electrode 30 are formed at each pixel P on the lower substrate 10. The thin film transistor T includes a gate electrode 14, a semiconductor layer 22, and source and drain electrodes 24 and 26. The semiconductor layer 22 is disposed over the gate electrode 14 with a gate insulating layer 20 therebetween. The source and drain electrodes 24 and 26 are formed on the semiconductor layer 22 and are spaced apart from each other.
The common electrode 18 includes a plurality of portions, and the pixel electrode 30 includes a plurality of parts. The portions of the common electrode 18 and the parts of the pixel electrode 30 are parallel to and spaced apart from each other on the lower substrate 10. The common electrode 18 may be formed of the same material and in the same layer as the gate electrode 14. The pixel electrode 30 may be formed of the same material and in the same layer as the source and drain electrodes 24 and 26.
Although not shown in the figure, a gate line is formed along a first side of the pixel P, and a data line is formed along a second side of the pixel P perpendicular to the first side. A common line is further formed on the lower substrate 10. The common line provides the common electrode 18 with a voltage.
A black matrix 42 and a color filter layer 44 are formed on an inner surface of the upper substrate 40. The black matrix 42 is disposed over the gate line, the data line and the thin film transistor T. The color filter layer 44 is disposed at the pixel P.
Liquid crystal molecules of the liquid crystal layer LC are driven by a horizontal electric field 35 induced between the common electrode 18 and the pixel electrodes 30.
The lower substrate 10 including the thin film transistor T, the common electrode 18 and the pixel electrode 30 may be referred to as an array substrate. The upper substrate 40 including the black matrix 42 and the color filter layer 44 may be referred to as a color filter substrate.
FIG. 2 is a schematic plan view of an array substrate for an IPS mode LCD device according to the related art.
In FIG. 2, a gate line 12 is formed on a substrate 10, and a data line 28 crosses the gate line 12 to define a pixel region P. A common line 16 is parallel to and spaced apart from the gate line 12. The common line 16 goes across the pixel region P. A thin film transistor T is formed at a crossing point of the gate line 12 and the data line 28. The thin film transistor T includes a gate electrode 14, a semiconductor layer 22, and source and drain electrodes 24 and 26. The gate electrode 14 is connected to the gate line 12. The semiconductor layer 22 is disposed over the gate electrode 14. The source and drain electrodes 24 and 26 are disposed on the semiconductor layer 22 and are spaced apart from each other.
A common electrode 18 extends from the common line 16 and is formed in the pixel region P. The common electrode 18 includes a plurality of portions, which are parallel to and spaced apart from each other. A pixel electrode 30 is formed in the pixel region P. The pixel electrode 30 includes a plurality of parts, which are parallel to and alternate with the portions of the common electrode 18.
An IPS mode LCD device having the array substrate of the above-mentioned structure has relatively wide viewing angles in a left-right direction with respect to the device, but still has narrow viewing angles in an up-down direction or a diagonal direction with respect to the device.
To increase the viewing angles in the up-down or diagonal direction, another structure has been proposed.
FIG. 3 is a plan view of an array substrate for an IPS mode LCD device according to another embodiment of the related art.
In FIG. 3, a gate line 52 is formed along a first direction on a substrate 50. A date line 66 is formed along a second direction. The data line 66 crosses the gate line 52 to define a pixel region P. A thin film transistor T is formed at a crossing point of the gate and data lines 52 and 66. A common electrode 56 and a pixel electrode 72 are formed in the pixel region P.
The thin film transistor T includes a gate electrode 54, an active layer 60, a source electrode 62 and a drain electrode 64. The gate electrode 54 is connected to the gate line 52. The active layer 60 is formed over the gate electrode 54 with a gate insulating layer (not shown) therebetween. The source and drain electrodes 62 and 64 are spaced apart from each other over the active layer 60. The source electrode 62 is connected to the data line 66.
The common electrode 56 is formed of the same material and in the same layer as the gate line 52. The gate insulating layer (not shown) and a passivation layer (not shown) are formed between the common electrode 56 and the pixel electrode 72 to prevent the pixel electrode 72 from contacting the common electrode 56. The pixel electrode 72 is formed of a transparent conductive material to increase an aperture ratio. The pixel electrode 72 may be formed of the same material and in the same layer as the source and drain electrodes 62 and 64.
The common electrode 56 includes horizontal portions 56a, a first vertical portion 56b and a second vertical portion 56c. The horizontal portions 56a are formed along the first direction and are spaced apart from each other. The first vertical portion 56b is connected to one ends of the horizontal portions 56a, and the second vertical portion 56c is connected to the other ends of the horizontal portions 56a. The pixel electrode 72 includes horizontal parts 72a, a first vertical part 72b, and a second vertical part 72c. The horizontal parts 72a are formed along the first direction and alternate with the horizontal portions 56a. The first vertical part 72b is connected to one ends of the horizontal parts 72a, and the second vertical part 72c is connected to the other ends of the horizontal parts 72a. 
Since the common electrode 56 and the pixel electrode 72 are arranged along the first direction, that is, substantially horizontally, the viewing angles are increased in the up-down direction. If the common and pixel electrodes 56 and 72 are inclined with a predetermined angle with respect to the first direction, the viewing angles may be increased in the diagonal direction.
However, the common electrode 56 and the pixel electrode 72 are formed in difference layers, and the common electrode 56 and the pixel electrode 72 may be misaligned during respective processes. The misalignment lowers image qualities of the device.
FIG. 4 is a cross-sectional view of an array substrate for an IPS mode LCD device according to another embodiment of the related art.
In FIG. 4, horizontal portions 56a of a common electrode are formed on a substrate 50. A gate insulating layer 58 and a passivation layer 68 are sequentially formed on the horizontal portions 56a of the common electrode. Horizontal parts 72a of a pixel electrode are formed on the passivation layer 68. Each of the horizontal parts 72a is disposed between adjacent horizontal portions 56a. 
After the horizontal portions 56a are patterned through a mask process, the horizontal parts 72a of the pixel electrode are patterned through another mask process. Each mask process includes a light-exposing step. A substrate is repeatedly exposed to light, moving with respect to a mask because the mask is relatively very small in comparison with the substrate. Thus, during the light-exposing step, the mask may be misaligned with the substrate.
As shown in FIG. 4, there is no misalignment in a first area NA. However, when a second area ANA is exposed to light in order to form the pixel electrode, the mask may be misaligned with the substrate 50. A distance L1 between the common electrode and the pixel electrode in the first area NA is not equal to a distance L2 between the common electrode and the pixel electrode. Accordingly, the quality of displayed images is not uniform in some areas.
Moreover, since the common electrode is formed of an opaque material, the brightness of the device is relatively low.